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4.5 r on , 4-/8-channel 5 v,+12 v, +5 v, and +3.3 v multiplexers ADG1608/adg1609 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2009 analog devices, inc. all rights reserved. features 4.5 typical on resistance 1 on-resistance flatness up to 470 ma continuous current 3.3 v to 8 v dual-supply operation 3.3 v to 16 v single-supply operation no v l supply required 3 v logic-compatible inputs rail-to-rail operation 16-lead tssop and 16-lead, 3 mm 3 mm lfcsp applications communication systems medical systems audio signal routing video signal routing automatic test equipment data acquisition systems battery-powered systems sample-and-hold systems relay replacements functional block diagrams ADG1608 1-of-8 decoder a0 a1 a2 en s1 s8 d 08318-001 figure 1. adg1609 1-of-4 decoder a0 a1 en s1a da db s4a s 1b s 4b 08318-002 figure 2. general description the ADG1608/adg1609 are monolithic cmos analog multip- lexers comprising eight single channels and four differential channels, respectively. the ADG1608 switches one of eight inputs to a common output, as determined by the 3-bit binary address lines, a0, a1, and a2. the adg1609 switches one of four differential inputs to a common differential output, as determined by the 2-bit binary address lines, a0 and a1. an en input on both devices is used to enable or disable the device. when disabled, all channels are switched off. each switch conducts equally well in both directions when on and has an input signal range that extends to the supplies. in the off condition, signal levels up to the supplies are blocked. all switches exhibit break-before-make switching action. inherent in the design is low charge injection for minimum transients when switching the digital inputs. the low on resistance of these switches make them ideal solu- tions for data acquisition and gain switching applications where low on resistance and distortion is critical. the on-resistance profile is very flat over the full analog input range, ensuring excellent linearity and low distortion when switching audio signals. cmos construction ensures ultralow power dissipation, making the parts ideally suited for portable and battery- powered instruments. product highlights 1. 8 maximum on resistance over temperature. 2. minimum distortion: thd + n = 0.04% 3. 3 v logic-compatible digital inputs: v inh = 2.0 v, v inl = 0.8 v. 4. no v l logic power supply required. 5. ultralow power dissipation: <8 nw. 6. 16-lead tssop and 16-lead, 3 mm 3 mm lfcsp.
ADG1608/adg1609 rev. 0 | page 2 of 20 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagrams ............................................................. 1 general description ......................................................................... 1 product highlights ........................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 5 v dual supply ......................................................................... 3 12 v single supply ........................................................................ 4 5 v single supply .......................................................................... 4 3.3 v single supply ....................................................................... 6 continuous current per channel, s or d ..................................7 absolute maximum ratings ............................................................8 esd caution...................................................................................8 pin configurations and function descriptions ............................9 typical performance characteristics ........................................... 11 test circuits ..................................................................................... 14 terminology .................................................................................... 17 outline dimensions ....................................................................... 18 ordering guide .......................................................................... 18 revision history 7/09revision 0: initial version
ADG1608/adg1609 rev. 0 | page 3 of 20 specifications 5 v dual supply v dd = +5 v 10%, v ss = ?5 v 10%, gnd = 0 v, unless otherwise noted. table 1. parameter 25c ?40c to +85c ?40c to +125c unit test conditions/comments analog switch analog signal range v dd to v ss v on resistance (r on ) 4.5 typ v s = 4.5 v, i s = ?10 ma; see figure 25 5 7 8 max v dd = 4.5 v, v ss = 4.5 v on-resistance match between channels (?r on ) 0.12 typ v s = 4.5 v, i s = ?10 ma 0.25 0.3 0.35 max on-resistance flatness (r flat(on) ) 1 typ v s = 4.5 v, i s = ?10 ma 1.3 1.7 2 max leakage currents v dd = +5.5 v, v ss = ?5.5 v source off leakage, i s (off) 0.02 na typ v s = 4.5 v, v d = ? 4.5 v; see figure 26 0.1 0.5 3 na max drain off leakage, i d (off) 0.03 na typ v s = 4.5 v, v d = ? 4.5 v; see figure 26 ADG1608 0.15 2 14 na max adg1609 0.15 1 7 na max channel on leakage, i d , i s (on) 0.03 na typ v s = v d = 4.5 v; see figure 27 0.15 2 14 na max digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.8 v max input current, i inl or i inh 1 na typ v in = v gnd or v dd 0.1 a max digital input capacitance, c in 4 pf typ dynamic characteristics 1 transition time, t transition 150 ns typ r l = 300 , c l = 35 pf 182 230 258 ns max v s = 2.5 v; see figure 28 t on (en) 106 ns typ r l = 300 , c l = 35 pf 132 150 160 ns max v s = 2.5 v; see figure 30 t off (en) 113 ns typ r l = 300 , c l = 35 pf 144 178 202 ns max v s = 2.5 v; see figure 30 break-before-make time delay, t d 47 ns typ r l = 300 , c l = 35 pf 30 ns min v s1 = v s2 = 2.5 v; see figure 29 charge injection 24 pc typ v s = 0 v, r s = 0 , c l = 1 nf; see figure 31 off isolation ?64 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 32 channel-to-channel crosstalk ?64 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 34 total harmonic distortion + noise (thd + n) 0.04 % typ r l = 110 , v s = 5 v p-p, f = 20 hz to 20 khz; see figure 35 ?3 db bandwidth r l = 50 , c l = 5 pf; see figure 33 ADG1608 40 mhz typ adg1609 71 mhz typ c s (off) 20 pf typ v s = 0 v, f = 1 mhz c d (off) ADG1608 120 pf typ v s = 0 v, f = 1 mhz adg1609 61 pf typ v s = 0 v, f = 1 mhz c d , c s (on) ADG1608 153 pf typ v s = 0 v, f = 1 mhz adg1609 85 pf typ v s = 0 v, f = 1 mhz power requirements v dd = +5.5 v, v ss = ?5.5 v i dd 0.001 a typ digital inputs = 0 v or v dd 1.0 a max v dd /v ss 3.3/8 v min/max 1 guaranteed by design, but not subject to production test.
ADG1608/adg1609 rev. 0 | page 4 of 20 12 v single supply v dd = 12 v 10%, v ss = 0 v, gnd = 0 v, unless otherwise noted. table 2. parameter 25c ?40c to +85c ?40c to +125c unit test conditions/comments analog switch analog signal range 0 v to v dd v on resistance (r on ) 4 typ v s = 0 v to 10 v, i s = ?10 ma; see figure 25 4.5 6.5 7.5 max v dd = 10.8 v, v ss = 0 v on-resistance match between channels (?r on ) 0.12 typ v s = 10 v, i s = ?10 ma 0.25 0.3 0.35 max on-resistance flatness (r flat(on) ) 0.9 typ v s = 0 v to 10 v, i s = ?10 ma 1.2 1.6 1.9 max leakage currents v dd = 13.2 v, v ss = 0 v source off leakage, i s (off) 0.02 na typ v s = 1 v/10 v, v d = 10 v/1 v; see figure 26 0.1 0.5 3 na max drain off leakage, i d (off) 0.03 na typ v s = 1 v/10 v, v d = 10 v/1 v; see figure 26 ADG1608 0.15 2 14 na max adg1609 0.15 1 7 na max channel on leakage, i d , i s (on) 0.03 na typ v s = v d = 1 v or 10 v; see figure 27 0.15 2 14 na max digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.8 v max input current, i inl or i inh 1 na typ v in = v gnd or v dd 0.1 a max digital input capacitance, c in 4 pf typ dynamic characteristics 1 transition time, t transition 113 ns typ r l = 300 , c l = 35 pf 141 172 196 ns max v s = 8 v; see figure 28 t on (en) 80 ns typ r l = 300 , c l = 35 pf 94 101 110 ns max v s = 8 v; see figure 30 t off (en) 77 ns typ r l = 300 , c l = 35 pf 93 117 140 ns max v s = 8 v; see figure 30 break-before-make time delay, t d 47 ns typ r l = 300 , c l = 35 pf 30 ns min v s1 = v s2 = 8 v; see figure 29 charge injection 29 pc typ v s = 6 v, r s = 0 , c l = 1 nf; see figure 31 off isolation ?64 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 32 channel-to-channel crosstalk ?64 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 34 total harmonic distortion + noise (thd + n) 0.04 % typ r l = 110 , v s = 5 v p-p, f = 20 hz to 20 khz; see figure 35 ?3 db bandwidth r l = 50 , c l = 5 pf; see figure 33 ADG1608 40 mhz typ adg1609 78 mhz typ c s (off) 19 pf typ v s = 6 v, f = 1 mhz c d (off) ADG1608 117 pf typ v s = 6 v, f = 1 mhz adg1609 59 pf typ v s = 6 v, f = 1 mhz c d , c s (on) ADG1608 149 pf typ v s = 6 v, f = 1 mhz adg1609 84 pf typ v s = 6 v, f = 1 mhz power requirements v dd = 12 v i dd 0.001 a typ digital inputs = 0 v or v dd 1.0 a max ADG1608 300 a typ digital inputs = 5 v 480 a max adg1609 225 a typ digital inputs = 5 v 360 a max v dd 3.3/16 v min/max 1 guaranteed by design, but not subject to production test.
ADG1608/adg1609 rev. 0 | page 5 of 20 5 v single supply v dd = 5 v 10%, v ss = 0 v, gnd = 0 v, unless otherwise noted. table 3. parameter 25c ?40cto +85c ?40c to +125c unit test conditions/comments analog switch analog signal range 0 v to v dd v on resistance (r on ) 8.5 typ v s = 0 v to 4.5 v, i s = ?10 ma; see figure 25 10 12.5 14 max v dd = 4.5 v, v ss = 0 v on-resistance match between channels (?r on ) 0.15 typ v s = 0 v to 4.5 v, i s = ?10 ma 0.3 0.35 0.4 max on-resistance flatness (r flat(on) ) 1.7 typ v s = 0 v to 4.5 v, i s = ?10 ma 2.3 2.7 3 max leakage currents v dd = 5.5 v, v ss = 0 v source off leakage, i s (off) 0.01 na typ v s = 1 v/4.5 v, v d = 4.5 v/1 v; see figure 26 0.1 0.5 3 na max drain off leakage, i d (off) 0.01 na typ v s = 1 v/4.5 v, v d = 4.5 v/1 v; see figure 26 ADG1608 0.15 2 14 na max adg1609 0.15 1 7 na max channel on leakage, i d , i s (on) 0.01 na typ v s = v d = 1 v or 4.5 v; see figure 27 0.15 2 14 na max digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.8 v max input current, i inl or i inh 1 na typ v in = v gnd or v dd 0.1 a max digital input capacitance, c in 4 pf typ dynamic characteristics 1 transition time, t transition 193 ns typ r l = 300 , c l = 35 pf 251 301 339 ns max v s = 2.5 v; see figure 28 t on (en) 115 ns typ r l = 300 , c l = 35 pf 152 171 184 ns max v s = 2.5 v; see figure 30 t off (en) 140 ns typ r l = 300 , c l = 35 pf 184 225 259 ns max v s = 2.5 v; see figure 30 break-before-make time delay, t d 66 ns typ r l = 300 , c l = 35 pf 37 ns min v s1 = v s2 = 2.5 v; see figure 29 charge injection 11 pc typ v s = 2.5 v, r s = 0 , c l = 1 nf; see figure 31 off isolation ?64 db typ r l = 50 , c l = 5 pf, f = 100 khz; see figure 32 channel-to-channel crosstalk ?64 db typ r l = 50 , c l = 5 pf, f = 100 khz; see figure 34 total harmonic distortion + noise (thd + n) 0.3 % typ r l = 110 , f = 20 hz to 20 khz, v s = 3.5 v p-p; see figure 35 ?3 db bandwidth r l = 50 , c l = 5 pf; see figure 33 ADG1608 37 mhz typ adg1609 72 mhz typ c s (off) 22 pf typ v s = 2.5 v, f = 1 mhz c d (off) v s = 2.5 v, f = 1 mhz ADG1608 136 pf typ adg1609 68 pf typ c d , c s (on) v s = 2.5 v, f = 1 mhz ADG1608 168 pf typ adg1609 94 pf typ power requirements v dd = 5.5 v i dd 0.001 a typ digital inputs = 0 v or v dd 1.0 a max v dd 3.3/16 v min/max 1 guaranteed by design, but not subject to production test.
ADG1608/adg1609 rev. 0 | page 6 of 20 3.3 v single supply v dd = 3.3 v, v ss = 0 v, gnd = 0 v, unless otherwise noted. table 4. parameter 25c ?40c to +85c ?40c to +125c unit test conditions/comments analog switch analog signal range 0 v to v dd v on resistance (r on ) 13.5 15 16.5 typ v s = 0 v to v dd , i s = ?10 ma; see figure 25 , v dd = 3.3 v, v ss = 0 v on-resistance match between channels (?r on ) 0.25 0.28 0.3 typ v s = 0 v to v dd , i s = ?10 ma on-resistance flatness (r flat(on) ) 5 5.5 6.5 typ v s = 0 v to v dd , i s = ?10 ma leakage currents v dd = 3.6 v, v ss = 0 v source off leakage, i s (off) 0.01 na typ v s = 0.6 v/3 v, v d = 3 v/0.6 v; see figure 26 0.1 0.5 3 na max drain off leakage, i d (off) 0.01 na typ v s = 0.6 v/3 v, v d = 3 v/0.6 v; see figure 26 ADG1608 0.15 2 14 na max adg1609 0.15 1 7 na max channel on leakage, i d , i s (on) 0.01 na typ v s = v d = 0.6 v or 3 v; see figure 27 0.15 2 14 na max digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.8 v max input current, i inl or i inh 1 na typ v in = v gnd or v dd 0.1 a max digital input capacitance, c in 4 pf typ dynamic characteristics 1 transition time, t transition 312 ns typ r l = 300 , c l = 35 pf 437 498 542 ns max v s = 1.5 v; see figure 28 t on (en) 216 ns typ r l = 300 , c l = 35 pf 309 331 344 ns max v s = 1.5 v; see figure 30 t off (en) 236 ns typ r l = 300 , c l = 35 pf 316 367 411 ns max v s = 1.5 v; see figure 30 break-before-make time delay, t d 104 ns typ r l = 300 , c l = 35 pf 48 ns min v s1 = v s2 = 1.5 v; see figure 29 charge injection 6 pc typ v s = 1.5 v, r s = 0 , c l = 1 nf; see figure 31 off isolation ?64 db typ r l = 50 , c l = 5 pf, f = 100 khz; see figure 32 channel-to-channel crosstalk ?64 db typ r l = 50 , c l = 5 pf, f = 100 khz; see figure 34 total harmonic distortion + noise (thd + n) 0.5 % typ r l = 110 , f = 20 hz to 20 khz, v s = 2 v p-p; see figure 35 ?3 db bandwidth r l = 50 , c l = 5 pf; see figure 33 ADG1608 34 mhz typ adg1609 72 mhz typ c s (off) 23 pf typ v s = 1.5 v, f = 1 mhz c d (off) v s = 1.5 v, f = 1 mhz ADG1608 145 pf typ adg1609 72 pf typ c d , c s (on) v s = 1.5 v, f = 1 mhz ADG1608 173 pf typ adg1609 95 pf typ power requirements v dd = 3.6 v i dd 0.001 a typ digital inputs = 0 v or v dd 1.0 a max v dd 3.3/16 v min/max 1 guaranteed by design, but not subject to production test.
ADG1608/adg1609 rev. 0 | page 7 of 20 continuous current per channel, s or d table 5. ADG1608 parameter 25c 85c 125c unit continuous current, s or d v dd = +5 v, v ss = ?5 v tssop ( ja = 112.6c/w) 290 180 100 ma max lfcsp ( ja = 48.7c/w) 470 255 120 ma max v dd = 12 v, v ss = 0 v tssop ( ja = 112.6c/w) 213 129 73 ma max lfcsp ( ja = 48.7c/w) 346 185 84 ma max v dd = 5 v, v ss = 0 v tssop ( ja = 112.6c/w) 157 101 63 ma max lfcsp ( ja = 48.7c/w) 252 150 77 ma max v dd = 3.3 v, v ss = 0 v tssop ( ja = 112.6c/w) 126 87 56 ma max lfcsp ( ja = 48.7c/w) 206 129 73.5 ma max table 6. adg1609 parameter 25c 85c 125c unit continuous current, s or d v dd = +5 v, v ss = ?5 v tssop ( ja = 112.6c/w) 147 98 63 ma max lfcsp ( ja = 48.7c/w) 245 147 77 ma max v dd = 12 v, v ss = 0 v tssop ( ja = 112.6c/w) 157 101 63 ma max lfcsp ( ja = 48.7c/w) 255 150 77 ma max v dd = 5 v, v ss = 0 v tssop ( ja = 112.6c/w) 115 80 52 ma max lfcsp ( ja = 48.7c/w) 189 119 70 ma max v dd = 3.3 v, v ss = 0 v tssop ( ja = 112.6c/w) 94 66 45 ma max lfcsp ( ja = 48.7c/w) 154 101 63 ma max
ADG1608/adg1609 rev. 0 | page 8 of 20 absolute maximum ratings t a = 25c, unless otherwise noted. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 7. parameter rating v dd to v ss 18 v v dd to gnd ?0.3 v to +18 v v ss to gnd +0.3 v to ?18 v analog inputs 1 v ss ? 0.3 v to v dd + 0.3 v or 30 ma, whichever occurs first digital inputs 1 gnd ? 0.3 v to v dd + 0.3 v or 30 ma, whichever occurs first peak current, s or d 710 ma (pulsed at 1 ms, 10% duty cycle maximum) continuous current, s or d 2 data + 15% operating temperature range industrial (y version) ?40c to +125c storage temperature range ?65c to +150c junction temperature 150c 16-lead tssop, ja thermal impedance, 0 airflow (4-layer board) 112.6c/w 16-lead lfcsp, ja thermal impedance, 0 airflow (4-layer board) 48.7c/w reflow soldering peak temperature, pb free 260c esd caution 1 overvoltages at in, s, or d are clamped by internal diodes. current should be limited to the maximum ratings given. 2 see table 5 and table 6.
ADG1608/adg1609 rev. 0 | page 9 of 20 pin configurations and function descriptions 1 2 3 4 5 6 7 8 en v ss s1 s4 s3 s2 a0 d 16 15 14 13 12 11 10 9 a2 gnd v dd s7 s8 s6 s5 a1 ADG1608 top view (not to scale) 0 8318-003 figure 3. ADG1608 pin configuration (tssop) 08318-004 pin 1 indicator 1 v ss 2 s1 3 s2 4 s3 11 v dd 12 gnd 10 s5 9s6 5 s 4 6 d 7 s 8 8 s 7 1 5 a 0 1 6 e n 1 4 a 1 1 3 a 2 top view (not to scale) ADG1608 notes 1. the exposed pad is connected internally. for increased reliability of the solder joints and maximum thermal capability, it is recommended that the pad be soldered to the substrate, v ss . figure 4. ADG1608 pin configuration (lfcsp) table 8. ADG1608 pin function descriptions pin no. tssop lfcsp mnemonic description 1 15 a0 logic control input. 2 16 en active high digital input. when this pin is low, the devi ce is disabled and all switches are off. when this pin is high, ax logic inputs determine on switches. 3 1 v ss most negative power supply potential. in single-supply applications, this pin can be connected to ground. 4 2 s1 source terminal 1. can be an input or an output. 5 3 s2 source terminal 2. can be an input or an output. 6 4 s3 source terminal 3. can be an input or an output. 7 5 s4 source terminal 4. can be an input or an output. 8 6 d drain terminal. can be an input or an output. 9 7 s8 source terminal 8. can be an input or an output. 10 8 s7 source terminal 7. can be an input or an output. 11 9 s6 source terminal 6. can be an input or an output. 12 10 s5 source terminal 5. can be an input or an output. 13 11 v dd most positive power supply potential. 14 12 gnd ground (0 v) reference. 15 13 a2 logic control input. 16 14 a1 logic control input. n/a ep ep exposed pad. the exposed pad is connected internally. for increased reliability of the solder joints and maximum thermal capability, it is recommended th at the pad be soldered to the substrate, v ss . table 9. ADG1608 truth table a2 a1 a0 en on switch x 1 x 1 x 1 0 none 0 0 0 1 1 0 0 1 1 2 0 1 0 1 3 0 1 1 1 4 1 0 0 1 5 1 0 1 1 6 1 1 0 1 7 1 1 1 1 8 1 x = dont care.
ADG1608/adg1609 rev. 0 | page 10 of 20 1 2 3 4 5 6 7 8 en v ss s1a s4a s3a s2a a0 da 16 15 14 13 12 11 10 9 gnd v dd s1b s4b db s3b s2b a1 adg1609 top view (not to scale) 0 8318-005 figure 5. adg1609 pin configuration (tssop) 08318-006 pin 1 indicator 1v ss 2 s1a 3 s2a 4 s3a 11 s1b 12 v dd 10 s2b 9s3b 5 s 4 a 6 d a 7 s b 8 s 4 b 1 5 a 0 1 6 e n 1 4 a 1 1 3 g n d top view (not to scale) adg1609 notes 1. the exposed pad is connected internally. for increased reliability of the solder joints and maximum thermal capability, it is recommended that the pad be soldered to the substrate, v ss . figure 6. adg1609 pin configuration (lfcsp) table 10. adg1609 pin function descriptions pin no. tssop lfcsp nemonic description 1 15 a0 logic control input. 2 16 en active high digital input. when this pin is low, the devi ce is disabled and all switches are off. when this pin is high, ax logic inputs determine on switches. 3 1 v ss most negative power supply potential. in single-supply applications, this pin can be connected to ground. 4 2 s1a source terminal 1a. ca n be an input or an output. 5 3 s2a source terminal 2a. ca n be an input or an output. 6 4 s3a source terminal 3a. ca n be an input or an output. 7 5 s4a source terminal 4a. ca n be an input or an output. 8 6 da drain terminal a. can be an input or an output. 9 7 db drain terminal b. can be an input or an output. 10 8 s4b source terminal 4b. ca n be an input or an output. 11 9 s3b source terminal 3b. ca n be an input or an output. 12 10 s2b source terminal 2b. can be an input or an output. 13 11 s1b source terminal 1b. can be an input or an output. 14 12 v dd most positive power supply potential. 15 13 gnd ground (0 v) reference. 16 14 a1 logic control input. n/a ep ep exposed pad. the exposed pad is connected internally. for increased reliability of the solder joints and maximum thermal capability, it is recommended th at the pad be soldered to the substrate, v ss . table 11. adg1609 truth table a1 a0 en on switch pair x 1 x 1 0 none 0 0 1 1 0 1 1 2 1 0 1 3 1 1 1 4 1 x = dont care.
ADG1608/adg1609 rev. 0 | page 11 of 20 typical performance characteristics 0 1 2 3 4 5 6 7 ?8 ?6 ?4 ?2 0 2 4 6 8 on resistance ( ? ) source or drain voltage (v) t a = 25c v dd = +8v v ss = ?8v v dd = +5v v ss = ?5v v dd = +3.3v v ss = ?3.3v 08318-029 figure 7. on resistance vs. v d (v s ) for dual supply 0 2 4 6 8 10 12 14 16 0 2 4 6 810 12 14 16 on resistance ( ? ) source or drain voltage (v) t a = 25c v dd = 16v v ss = 0v v dd = 12v v ss = 0v v dd = 5v v ss = 0v v dd = 3.3v v ss = 0v 08318-030 figure 8. on resistance vs. v d (v s ) for single supply 0 1 2 3 4 5 6 7 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 on resistance ( ? ) source or drain voltage (v) v dd = +5v v ss = ?5v t a = +125c t a = +85c t a = +25c t a = ?40c 0 8318-031 figure 9. on resistance vs. v d (v s ) for different temperatures, 5 v dual supply 0 1 2 3 4 5 6 7 024681012 on resistance ( ? ) source or drain voltage (v) t a = +125c t a = +85c t a = +25c t a = ?40c v dd = 12v v ss = 0v 0 8318-032 figure 10. on resistance vs. v d (v s ) for different temperatures, 12 v single supply 0 2 4 6 8 10 12 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 on resistance ( ? ) source or drain voltage (v) v dd = 5v v ss = 0v t a = +125c t a = +85c t a = +25c t a = ?40c 08318-033 figure 11. on resistance vs. v d (v s ) for different temperatures, 5 v single supply 0 2 4 6 8 10 12 14 16 18 0 0.5 1.0 1.5 2.0 2.5 3.0 on resistance ( ? ) source or drain voltage (v) v dd = 3.3v v ss = 0v t a = +125c t a = +85c t a = +25c t a = ?40c 08318-020 figure 12. on resistance vs. v d (v s ) for different temperatures, 3.3 v single supply
ADG1608/adg1609 rev. 0 | page 12 of 20 20 40 60 80 100 120 leakage current (na) temperature (c) 10 8 6 4 2 0 0 ?2 ?4 ?6 12 ?8 v dd = +5v v ss = ?5v v bias = +4.5v/?4.5v i d (off) ? + i d , i s (on) + + i s (off) + ? i d , i s (on) ? ? i s (off) ? + i d (off) + ? 0 8318-035 figure 13. ADG1608 leakage currents vs. temperature, 5 v dual supply 0 20406080100120 leakage current (na) temperature (c) 15 0 ?10 ?5 10 5 v dd = 12v v ss = 0v v bias = 1v/10v i d , i s (on) + + i d (off) ? + i s (off) + ? i d , i s (on) ? ? i s (off) ? + i d (off) + ? 08318-034 figure 14. ADG1608 leakage currents vs. temperature, 12 v single supply 0 20 40 60 80 100 120 leakage current (na) temperature (c) 10 9 5 1 ?1 0 7 8 3 4 2 6 v dd = 5v v ss = 0v v bias = 1v/4.5v i d , i s (on) + + i d (off) ? + i d , i s (on) ? ? i s (off) + ? i s (off) ? + i d (off) + ? 08318-036 figure 15.ADG1608 leakage currents vs. temperature, 5 v single supply 0 20406080100120 leakage current (na) temperature (c) 9 5 1 ?1 0 7 8 3 4 2 6 v dd = 3.3v v ss = 0v v bias = 0.6v/3v i d , i s (on) + + i d (off) ? + i d , i s (on) ? ? i s (off) + ? i d (off) + ? i s (off) ? + 08318-018 figure 16. ADG1608 leakage currents vs. temperature, 3.3 v single supply 02468101214 logic (v) 100 0 300 200 400 500 600 i dd (a) i dd per channel t a = 25c i dd = +3.3v i ss = 0v i dd = +5v i ss = 0v i dd = +5v i ss = ?5v i dd = +12v i ss = 0v 08318-019 figure 17. i dd vs. logic level 0 5 10 15 20 25 30 ?6 ?4 ?2 0 2 4 6 8 10 12 14 charge injection (pc) v s (v) v dd = +5v v ss = ?5v v dd = +5v v ss = 0v v dd = +3.3v v ss = 0v 08318-026 v ss = 0v v dd = +12v figure 18. charge injection vs. source voltage
ADG1608/adg1609 rev. 0 | page 13 of 20 0 50 100 150 200 250 300 350 400 450 ?40 ?20 0 20 40 60 80 100 120 transition time (ns) temperature (c) t a = 25c 0 8318-024 v dd = +3.3v, v ss = 0v v dd = +5v, v ss = 0v v dd = +5v, v ss = ?5v v dd = +12v, v ss = 0v figure 19. transition time vs. temperature ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 off isol a tion (db) frequency (hz) 10k 100k 1m 10m 100m 1g t a = 25c v dd = +5v v ss = ?5v 08318-023 figure 20. off isol ation vs. frequency ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 crosstalk (db) frequency (hz) 10k 100k 1m 10m 100m 1g t a = 25c v dd = +5v v ss = ?5v 08318-022 figure 21. crosstalk vs. frequency ?6 ?5 ?4 ?3 ?2 ?1 0 insertion loss (db) frequency (hz) 10k 100k 1m 10m 100m t a = 25c v dd = +5v v ss = ?5v 0 8318-021 figure 22. on response vs. frequency ?120 ?100 ?80 ?60 ?40 ?20 0 acpsrr (db) frequency (hz) 1k 1m 10m 100m 10k 100k t a = 25c v dd = +5v v ss = ?5v no decoupling capacitors decoupling capacitors 08318-027 figure 23. acpsrr vs. frequency 0 0.1 0.2 0.3 0.4 0.5 0.6 thd + n (%) frequency (hz) 5k 0 10k 15k 20k v dd = +3.3v, v s = 2v p-p v dd = +5v, v s = 3.5v p-p v dd = +5v, v ss = ?5v, v s = 5v p-p v dd = +12v, v s = 5v p-p load = 110 ? t a = 25c 08318-028 figure 24. thd + n vs. frequency
ADG1608/adg1609 rev. 0 | page 14 of 20 test circuits i ds sd v s v 08318-007 figure 25. on resistance sd v s a a v d i s (off) i d (off) 08318-008 figure 26. off leakage sd a v d i d (on) nc nc = no connect 08318-009 figure 27. on leakage 3v 0v output t r < 20ns t f < 20ns address drive (v in ) t transition t transition 50% 50% 90% 90% output ADG1608* a0 a1 a2 50? 100? gnd s1 s2 to s7 s8 d 35pf v in 2.4v en v dd v ss v dd v ss v s1 v s8 *similar connection for adg1609. 08318-010 figure 28. address to ou tput switching times, t transition output ADG1608* a0 a1 a2 50 ? 100 ? gnd s1 s2 to s7 s8 d 35pf v in 2.4v en v dd v ss v dd v ss v s *similar connection for adg1609. 3v 0v output 80% 80% a ddress drive (v in ) t bbm 08318-011 figure 29. break-before-make delay, t bbm
ADG1608/adg1609 rev. 0 | page 15 of 20 output ADG1608* a0 a1 a2 50 ? 100? gnd s1 s2 to s8 d 35pf v in en v dd v ss v dd v ss v s *similar connection for adg1609. 3v 0v output 50% 50% t off (en) t on (en) 0.9v o 0.9v o enable drive (v in ) 08318-012 figure 30. enable delay, t on (en), t off (en) 3v v in v out q inj = c l v out v out d s en gnd c l 1nf v out v in r s v s v dd v ss v dd v ss a0 a1 a2 ADG1608* *similar connection for adg1609. 08318-013 figure 31. charge injection
ADG1608/adg1609 rev. 0 | page 16 of 20 v out 50? network analyzer r l 50? s d 50? off isolation = 20 log v out v s v s v dd v ss 0.1f v dd 0.1f v ss gnd 08318-014 figure 32. off isolation v out 50? network analyzer r l 50 ? s d insertion loss = 20 log v out with switch v out without switch v s v dd v ss 0.1f v dd 0.1f v ss gnd 08318-016 figure 33. bandwidth channel-to-channel crosstalk = 20 log v out gnd s1 d s2 v out network analyzer r l 50? r 50? v s v s v dd v ss 0.1f v dd 0.1f v ss 08318-015 figure 34. channel-to-channel crosstalk v out r s audio precision r l 10k? in v in s d v s v p-p v dd v ss 0.1f v dd 0.1f v ss gnd 08318-017 figure 35. thd + noise
ADG1608/adg1609 rev. 0 | page 17 of 20 terminology i dd the positive supply current. i ss the negative supply current. v d (v s ) the analog voltage on terminal d and terminal s. r on the ohmic resistance between terminal d and terminal s. r flat(on) flatness that is defined as the difference between the maximum and minimum value of on resistance measured over the specified analog signal range. i s (off) the source leakage current with the switch off. i d (off) the drain leakage current with the switch off. i d , i s (on) the channel leakage current with the switch on. v inl the maximum input voltage for logic 0. v inh the minimum input voltage for logic 1. i inl (i inh ) the input current of the digital input. c s (off) the off switch source capacitance, which is measured with reference to ground. c d (off) the off switch drain capacitance, which is measured with reference to ground. c d , c s (on) the on switch capacitance, which is measured with reference to ground. c in the digital input capacitance. t transition the delay time between the 50% and 90% points of the digital input and switch on condition when switching from one address state to another. t on (en) the delay between applying the digital control input and the output switching on. t off (en) the delay between applying the digital control input and the output switching off . charge injection a measure of the glitch impulse transferred from the digital input to the analog output during switching. off isolation a measure of unwanted signal coupling through an off switch. crosstalk a measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. bandwidth the frequency at which the output is attenuated by 3 db. on response the frequency response of the on switch. insertion loss the loss due to the on resistance of the switch. total harmonic distortion + noise (thd + n) the ratio of the harmonic amplitude plus noise of the signal to the fundamental. ac power supply rejection ratio (acpsrr) the ratio of the amplitude of signal on the output to the amplitude of the modulation. this is a measure of the ability of the part to avoid coupling noise and spurious signals that appear on the supply voltage pin to the output of the switch. the dc voltage on the device is modulated by a sine wave of 0.62 v p-p.
ADG1608/adg1609 rev. 0 | page 18 of 20 outline dimensions 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153-ab figure 36. 16-lead thin shrink small outline package [tssop] (ru-16) dimensions shown in millimeters 3.10 3.00 sq 2.90 0.30 0.23 0.18 1.75 1.60 sq 1.55 070209-c 1 0.50 bsc bottom view top view 16 5 8 9 12 13 4 exposed pad p i n 1 i n d i c a t o r 0.50 0.40 0.30 seating plane 0.05 max 0.02 nom 0.20 ref 0.20 min coplanarity 0.08 pin 1 indicator forproperconnectionof the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.80 0.75 0.70 compliant to jedec standards mo-220-weed. figure 37. 16-lead lead frame chip scale package [lfcsp_wq] 3 mm x 3 mm body, very very thin quad (cp-16-22) dimensions shown in millimeters ordering guide model temperature range package description package option branding ADG1608bruz 1 ?40c to +125c 16-lead thin shrink small outline package [tssop] ru-16 ADG1608bruz-reel7 1 ?40c to +125c 16-lead thin shrink small outline package [tssop] ru-16 ADG1608bcpz-reel7 1 ?40c to +125c 16-lead lead frame chip scale package [lfcsp_wq] cp-16-22 s38 adg1609bruz 1 ?40c to +125c 16-lead thin shrink small outline package [tssop] ru-16 adg1609bruz-reel7 1 ?40c to +125c 16-lead thin shrink small outline package [tssop] ru-16 adg1609bcpz-reel7 1 ?40c to +125c 16-lead lead frame chip scale package [lfcsp_wq] cp-16-22 s39 1 z = rohs compliant part.
ADG1608/adg1609 rev. 0 | page 19 of 20 otes n
ADG1608/adg1609 rev. 0 | page 20 of 20 ?2009 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d08318-0-7/09(0) notes

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